The present invention relates to an array of memory cells for memory applications, and more particularly, to embodiments of a magnetic memory cell incorporating therein a magnetic memory element and dual selectors coupled thereto.
Spin transfer torque magnetic random access memory (STT-MRAM) is a new class of non-volatile memory, which can retain the stored information when powered off. An STT-MRAM device normally comprises an array of memory cells, each of which includes at least a magnetic memory element and a selection transistor coupled in series between appropriate electrodes. Upon application of a switching current to the magnetic memory element, the electrical resistance of the magnetic memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
FIG. 1 is a schematic circuit diagram of a conventional memory array 20, which comprises a plurality of memory cells 22 with each of the memory cells 22 including a selection transistor 24 coupled to a magnetic memory element 26; a plurality of parallel word lines 28 with each being coupled to the gates of a respective row of the selection transistors 24 in a first direction; a plurality of parallel bit lines 30 with each being coupled to a respective row of the magnetic memory elements 26 in a second direction substantially perpendicular to the first direction; and a plurality of parallel source lines 32 with each being coupled to a respective row of the selection transistors 24 in the first or second direction.
FIG. 2 shows a conventional memory element for the STT-MRAM device comprising a magnetic reference layer 50 and a magnetic free layer 52 with an insulating tunnel junction layer 54 interposed therebetween, thereby collectively forming a magnetic tunneling junction (MTJ) 56. The magnetic reference layer 50 and free layer 52 have magnetization directions 58 and 60, respectively, which are substantially perpendicular to the layer planes. Therefore, the MTJ 56 is a perpendicular type comprising the magnetic layers 50 and 52 with perpendicular anisotropy. Upon application of a switching current to the perpendicular MTJ 56, the magnetization direction 60 of the magnetic free layer 52 can be switched between two directions: parallel and anti-parallel with respect to the magnetization direction 58 of the magnetic reference layer 50. The insulating tunnel junction layer 54 is normally made of a dielectric material with a thickness ranging from a few to a few tens of angstroms. When the magnetization directions 60 and 58 of the magnetic free layer 52 and reference layer 50 are substantially parallel, electrons polarized by the magnetic reference layer 50 can tunnel through the insulating tunnel junction layer 54, thereby decreasing the electrical resistance of the perpendicular MTJ 56. Conversely, the electrical resistance of the perpendicular MTJ 56 is high when the magnetization directions 58 and 60 of the magnetic reference layer 50 and free layer 52 are substantially anti-parallel. Accordingly, the stored logic in the magnetic memory element can be switched by changing the magnetization direction 60 of the magnetic free layer 52.
The conventional memory array 20 for STT-MRAM illustrated in FIG. 1 is mostly limited to a single layer because the fabrication of the selection transistors 24 typically requires an epitaxial silicon substrate. Therefore, there is a need for an STT-MRAM cell that is stackable to form a three-dimensional memory array and that can be inexpensively manufactured.